Double-gate MOSFETs seem to be a very promising option for ultimate scaling of CMOS technology. Excellent short-channel effect (SCE) immunity, high transconductance, and ideal subthreshold performance have been reported from theoretical and experimental work on this device. Silicon-on-Insulator (SOI) technology can be considered as an alternative to conventional bulk MOSFET which can perform in a better way as expected from next generation Si technology. The continuous shrinking of Metal Oxide Semiconductor (MOS) device technology is facing countless challenges which have inspired the Engineers to focus on other promising devices. With the objective of diminishing different short channel effects (SCEs), various multigate devices have been proposed and are accounted to play a very vital role in deep submicron era due to better electrostatic control. Moreover, for transistor with reduced dimensions, it is very much troublesome tocreate ultra-sharp junctions in source/ drain, avoiding diffusion of impurities into the channel. This will enhance the complexity of fabrication process and hence further miniaturization is becoming a decisive challenge for device Engineers. Junctionless transistors with their pronounced electrostatic properties are flourished with the purpose to provide a partial solution for the above said challenging issue. Presently, double gate (DG) MOSFETs appear to be very convincing candidate for intense scaling of CMOS technology due to their excellent SCEs immunity, high transconductance and ideal subthreshold swing.