Digital Code Division Multiple Access .In CDMA allows many users to transmit and receive at the same time using a single channel. The transmitter and receiver are synchronized and synthesis carried out using VHDL tool shows increase in the overall speed of the system & the power consumption of the CDMA system will be reduced and error should not be introduce in this system. In past few years, lot of research is performed in both industries and academics into the development of CDMA. In CDMA multiple signal channels occupy the same frequency band being distinguished by the use of different spreading codes. Digital cellular telephone system and personal communication system uses CDMA communication. In this direct sequence spread spectrum principle based code division multiple access (CDMA) transmitter and receiver is implemented in VHDL for FPGA. The Xilinx synthesis technology of Xilinx ISE 9.2i tool will be used for synthesis of transmitter and receiver on FPGA Spartan3E. A transmitter and Receiver components have been designed individually using Bottom-up approach. The designs then are combined and defined by component declaration and port mapping. This work concentrates on application of VHDL simulation and FPGA compiler to Wireless Data components.